1. Field of the Invention
The invention relates to programmable memory arrays, and more particularly to systems and methods for reading memory cells in such an array.
2. Description of Related Art
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device comprises a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a bit line, and where each memory cell defines a binary bit, i.e., either a zero (“0”) bit or a one (“1”) bit. For example, a memory cell may be defined as either being a “programmed” cell or an “erased” cell, depending on the amount of charge stored on its floating gate. Depending on the convention chosen, an erased cell can represent a logic “1” and a programmed a logic “0,” or vice versa. In one type of memory cell, each cell stores two binary bits, a “left bit” and a “right bit.” The left bit can represent a “0” or a “1” while the right bit can represent a “0” or a “1” independent of the left bit.
Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell when the word line to which it is connected is brought to a particular voltage. For example, to ascertain the current drawn by a particular memory cell using drain-side sensing, the drain terminal of the memory cell is connected to a sensing circuit, the source terminal of the memory cell is connected to ground, and the word line to which the gate of the memory cell is connected is brought to a particular read voltage. The sensing circuit attempts to detect the current drawn by the memory cell, and compares the sensed memory cell current against a reference current. If the sensed memory cell current exceeds the reference current, the memory cell is considered to be in its erased state. If the sensed memory cell current is below the reference current, the memory cell is considered to be in its programmed state.
It is desirable to have the sensed memory cell current be greater than or less than the reference current by a “read margin.” As used herein, “read margin” is defined as the absolute value of the difference between current drawn by a target memory cell being read and the current drawn by a reference cell during a read operation. With a sufficient read margin, the impact of extraneous factors, such as noise, for example, upon the detection of the memory cell current is greatly reduced.
In some memory circuits, read margin is reduced due to leakage currents through cells neighboring the cell being read. To illustrate this, reference is made to FIGS. 1A, 1B and 2. FIG. 1A illustrates a known memory circuit 100 corresponding to a portion of a memory device. In circuit 100, bit lines 116 and 121 are connected through a selection circuit, generally shown as Y-Paths 166a and 166b, in a manner so as to sense memory cell current 110 drawn by target memory cell 105. This arrangement may be implemented when a read operation involving memory cell 105 is to be performed. Y-Paths 166a and 166b establish connections for bit lines 116 and 121, respectively, in circuit 100 and can, for brevity, be represented by simplified Y-Path 166 as shown in FIG. 1B. FIG. 1B depicts a simplified “Y-decoder” or “Y-select path,” referred to simply as “Y-Path” 166. In FIG. 1B, Y-Path 166 provides a connection between node 117 and node 118 through resistor 169, transistor 167, resistor 168, and transistor 164, when both transistors 167 and 164 are activated, e.g., by providing activation signals to respective gates of transistors 167 and 164. Resistors 168 and 169 represent resistance due to global metal bit lines and diffusion bit lines.
Continuing with FIG. 1A, bit line 121 is configured as a “drain” bit line (designated “D” in FIG. 1) by connecting node 123 to sensing circuit 160 through Y-Path 166b. Bit line 116 is configured as a “source” bit line (designated “S” in FIG. 1) by connecting node 117 to ground 165 through Y-Path 166a. Bit lines 141 and 151 are floating and may have a pattern-dependent path to ground through the neighboring memory cells. Word line 125 (designated “WL” in FIG. 1) is connected to the gate terminal of memory cell 105 and is utilized to activate memory cell 105. When memory cell 105 is activated, the amount of current 110 drawn by memory cell 105 indicates the “programmed” or “erased” status of memory cell 105. By way of illustration, if memory cell 105 is “programmed,” a low current, for example less 10 μA, is drawn by memory cell 105. Conversely, if memory cell 105 is “erased,” a high current, for example greater than 20 μA, is drawn by memory cell 105.
With memory circuit 100, sensing circuit 160 senses current 130 in an attempt to ascertain memory cell current 110 through memory cell 105. However, when memory cell 105 is a programmed cell, side leakage current 135 from node 123 to node 143 may be drawn when neighboring memory cell 155 and all its neighboring cells between memory cell 155 and ground are erased cells. Another potential source for leakage current 135 is transient current that could be present for charging some of the bit lines for memory cells situated on the right side of memory cell 155 in FIG. 1A. In this case, current 130 detected by sensing circuit 160 will be the sum of memory cell current 110 and leakage current 135, effectively raising current 130 and reducing the read margin during the read operation when memory cell 105 is a programmed cell. Reducing this read margin during a read operation reduces the reliability of the read operation.
FIG. 2 shows another known memory circuit 200 corresponding to a portion of a memory device. Similar to memory circuit 100 of FIG. 1, bit line 221 of memory cell 205 is configured as a “drain” bit line (designated “D” in FIG. 2) by connecting node 223 to sensing circuit 260 through Y-Path 266b, while bit line 216 is configured as a “source” bit line (designated “S” in FIG. 2) by connecting node 217 to ground 265 through Y-Path 266a, in a manner so as to sense memory cell current 210 drawn by memory cell 205. Word line 225 (designated “WL” in FIG. 2) is connected to the gate terminal of memory cell 205 and is utilized to activate memory cell 205. When memory cell 205 is activated, the amount of current 210 drawn by memory cell 205 indicates the “programmed” or “erased” status of memory cell 205.
In memory circuit 200, bit line 241 of neighboring cell 255 is configured as a “precharge” bit line (designated “P” in FIG. 2) by connecting node 243 to precharge circuit 280 through Y-Path 266c. Y-Paths 266a, 266b and 266c can be represented by Y-Path 166 as shown in FIG. 1B and described above.
Node 243 connected to bit line 241 is supplied a precharge voltage in an effort to reduce leakage current from node 223 to node 243 when target memory cell 205 is a programmed cell and neighboring memory cell 255 is an erased or over-erased cell. For example, precharge circuit 280 attempts to provide at node 243 a voltage at about the same level as that provided at node 223 by sensing circuit 260. In practice, however, the voltages at node 243 and at node 223 can vary significantly from each other, even when sensing circuit 260 and precharge circuit 280 are similarly designed. For example, the voltage difference between node 243 and node 223 may be as high as 50 millivolts (mV). Moreover, the difference in voltages between nodes 243 and 223 cannot be easily controlled and/or compensated for in memory circuit 200 because the difference in voltages at nodes 243 and 223 are due, in large part, to the different magnitudes of the currents drawn from sensing circuit 260 and precharge circuit 280, respectively, particularly when memory cell 205 is an erased cell and memory cell 255 is an erased or over-erased cell and memory cell 270 is a programmed cell.
Since the amount of current 210 drawn through memory cell 205 depends on whether memory cell 205 is an erased cell or a programmed cell, memory circuit 200 is unable to effectively control and compensate for the disparity in the currents drawn from sensing circuit 260 and precharge circuit 280, resulting in a significant voltage difference between nodes 243 and 223. Consequently, leakage current 235 from node 243 to node 223 is drawn through memory cell 255 in the case where memory cell 205 is an erased cell and neighboring memory cell 255 is an erased or over-erased cell and memory cell 270 is a programmed cell. The reason is that when memory cell 205 is an erased cell, memory cell current 210 acts to decrease the voltage supplied at node 223. As a result, the difference in voltages between nodes 243 and 223 acts to draw leakage current 235 from node 243 to node 223 through memory cell 255. In this case, sensing circuit 260 will sense current 230 corresponding to the difference between memory cell current 210 and leakage current 235, effectively reducing current 230 when memory cell 205 is an erased cell and thereby reducing the read margin during a read operation.
In U.S. Pat. No. 6,731,542, incorporated herein by reference, an attempt is made to solve this problem by connecting the sensing circuit not only to the drain of the target cell, but also to the drain of the first neighboring cell. Similarly, the precharge circuit is connected to both the drain of the second neighboring cell, beyond the first neighboring cell, and also to the drain of the third neighboring cell, beyond the second neighboring cell. In another embodiment, the sensing circuit is connected not only to the drain of the target cell, but also to the drains of each of the first two adjacent cells neighboring the target cell; and the precharge circuit is connected to the drains of each of the next three adjacent cells. Another attempt to solve the side current leakage problem appears in U.S. Pat. No. 6,771,543, also incorporated by reference herein, in which the node(s) to which the precharge voltage is connected are separated from the node(s) to which the sensing circuit is connected by one or more floating gates.
While many of the above techniques can help improve read margin by reducing side leakage currents, they do so at the expense of increased current draw for charging up additional drain (D) and precharge (P) bit lines in advance of each sense operation. It would be desirable to reduce the effective current draw while also gaining the benefits of reduced side leakage currents.